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PLDC20RA10
Reprogrammable Asynchronous CMOS Logic Device
1PLDC20RA10
Features
* * * * * * * * * Advanced-user programmable macrocell CMOS EPROM technology for reprogrammability Up to 20 input terms 10 programmable I/O macrocells Output macrocell programmable as combinatorial or asynchronous D-type registered output Product-term control of register clock, reset and set and output enable Register preload and power-up reset Four data product terms per output macrocell Fast -- Commercial tPD = 15 ns tCO = 15 ns tSU = 7 ns
-- ICC max = 85 mA (Military) * High reliability -- Proven EPROM technology -- >2001V input protection -- 100% programming and functional testing * Windowed DIP, windowed LCC, DIP, LCC, PLCC available
Functional Description
The Cypress PLDC20RA10 is a high-performance, second-generation programmable logic device employing a flexible macrocell structure that allows any individual output to be configured independently as a combinatorial output or as a fully asynchronous D-type registered output. The Cypress PLDC20RA10 provides lower-power operation with superior speed performance than functionally equivalent bipolar devices through the use of high-performance 0.8-micron CMOS manufacturing technology. The PLDC20RA10 is packaged in a 24 pin 300-mil molded DIP, a 300-mil windowed cerDIP, and a 28-lead square leadless chip carrier, providing up to 20 inputs and 10 outputs. When the windowed device is exposed to UV light, the 20RA10 is erased and can then be reprogrammed.
-- Military tPD = 20 ns tCO = 20 ns tSU = 10 ns * Low power -- ICC max - 80 mA (Commercial)
Logic Block Diagram
VSS 12 I9 11 I8 10 I7 9 I6 8 I5 7 I4 6 I3 5 I2 4 I1 3 I0 2 PL 1
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
13 OE
14 I/O9
15 I/O8
16 I/O7
17 I/O6
18 I/O5
19 I/O4
20 I/O3
21 I/O2
22 I/O1
23 I/O0 RA10-1
24 VCC
Cypress Semiconductor Corporation Document #: 38-03012 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised March 26, 1997
PLDC20RA10
Selection Guide
Generic Part Number 20RA10-15 20RA10-20 20RA10-25 20RA10-35 tPD ns Com`l 15 20 Mil 20 25 35 Com'l 7 10 tSU ns Mil 10 15 20 Com'l 15 20 tCO ns Mil 20 25 35 Com'l 80 80 tCC ns Mil 85 85 85
Pin Configurations
LCC Top View
NC I1 I0 PL V CC I/O0 I/O1
STD PLCC/HLCC Top View
PL V CC I/O0 I/O1 I2 I1 I0
JEDEC PLCC/HLCC Top View
PL NC VCC I/O0 I/O1 I1 I0
[1]
4 3 2 1 282726 I2 I3 I4 I5 I6 I 7 NC 5 6 7 8 9 10 11 25 24 23 22 21 20 19 NC I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NC I3 I4 NC I5 I6 NC 5 6 7 8 9 10 11
4 3 2 1 2827 26 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NC I2 I3 I4 NC I5 I6 I7 5 6 7 8 9 10 11
4 3 2 1 2827 26 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 NC I/O 5 I/O 6 I/O 7
PLDC20RA10
PLDC20RA10
PLDC20RA10 CG7C324
121314 1516 1718
12131415161718 8 9 V SS OE I/O9 I/O8 NC
121314 1516 1718 7
8 9 V SS OE I/O9 I/O8
RA10-2
RA10-3
8 9 V SS NC OE I/O9 I/O8
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell. The cell dedicates three product terms for fully asynchronous control of the register set, reset, and clock functions, as well as, one term for control of the output enable function. The output enable product term output is ANDed with the input from pin 13 to allow either product term or hardwired external control of the output or a combination of control from both sources. If product-term-only control is selected, it is automatically chosen for all outputs since, for this case, the external output enable pin must be tied LOW. The active polarity of each output may be programmed independently for each output cell and is subsequently fixed. Figure 2 illustrates the output enable options available. When an I/O cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term outputs to be HIGH under all input conditions. This is achieved by programming all input term programming cells for these two product terms. Figure 3 illustrates the available output configuration options. An additional four uncommitted product terms are provided in each output macrocell as resources for creation of user-defined logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input, the device input configuration programmed by the user may vary from a total of nine programmable plus ten dedicated inputs (a total of nineteen inputs) and one output down to a ten-input, ten-output configuration with all ten programmable I/O cells configured as outputs. Each input pin available in a given configuration is available as an input to the four control
Note: 1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The principal difference is in the location of the "no connect" (NC) pins
Document #: 38-03012 Rev. **
I I
I
I I
product terms and four uncommitted product terms of each programmable I/O macrocell that has been configured as an output. An I/O cell is programmed as an input by tying the output enable pin (pin 13) HIGH or by programming the output enable product term to provide a LOW, thereby disabling the output buffer, for all possible input combinations. When utilizing the I/O macrocell as an output, the input path functions as a feedback path allowing the output signal to be fed back as an input to the product term array. When the output cell is configured as a registered output, this feedback path may be used to feed back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each register to be set by loading each register from an external source prior to exercising the device. Testing of complex state machine designs is simplified by the ability to load an arbitrary state without cycling through long test vector sequences to reach the desired state. Recovery from illegal states can be verified by loading illegal states and observing recovery. Preload of a particular register is accomplished by impressing the desired state on the register output pin and lowering the signal level on the preload control pin (pin1) to a logic LOW level. If the specified preload set-up, hold and pulse width minimums have been observed, the desired state is loaded into the register. To insure predictable system initialization, all registers are preset to a logic LOW state upon power-up, thereby setting the active LOW outputs to a logic HIGH.
I I
RA10-4
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PLDC20RA10
.
PRELOAD (FROM PIN 1)
OUTPUT ENABLE (FROM PIN 13)
S D C0 PL P R Q
1S O
TO I/O PIN O
RA10-5
Figure 1. PLDC20RA10 Macrocell
Output Always Enabled
Programmable
RA10-6
RA10-7
External Pin
OE
Combination of Programmable and Hardwired
RA10-8
RA10-9
Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10
Document #: 38-03012 Rev. **
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PLDC20RA10
Registered/ActiveLOW
Combinatorial/Active LOW
S D Q
R
RA10-10
RA10-11
Registered/Active HIGH
Combinatorial/Active HIGH
S D Q
R
RA10-12
RA10-13
Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10
Document #: 38-03012 Rev. **
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PLDC20RA10
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 24 to Pin 12) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage......................................... -3.0 V to + 7.0 V Output Current into Outputs (LOW) .............................16 mA
]
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA DC Program Voltage .................................................... 13.0V
Operating Range
Range Commercial Military[2] Ambient Temperature 0C to +75C -55C to +125C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[3]
Parameter VOH VOL VIH VIL IIX IOZ ISC ICC1 ICC2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Output Short Circuit Current[5] Standby Power Supply Current Power Supply Current at Frequency[5] VCC = Min., VIN =VIH or VIL VCC = Min., VIN = VIH or VIL Test Conditions IOH = -3.2 mA IOH = -2 mA IOL = 8 mA 2.0 0.8 -10 -40 -30 Com'l Mil VCC = Max., Outputs Disabled (In High Z State) Device Operating at fMAX Com'l Mil +10 +40 -90 75 80 80 85 Com'l Mil 0.5 V V V A A mA mA mA mA mA Min. 2.4 Max. Unit V
Guaranteed Input Logical HIGH Voltage for All Inputs[4] Guaranteed Input Logical LOW Voltage for All Inputs VSS VIN VCC, VCC = Max VCC = Max., VSS VOUT VCC VCC = Max., VOUT = 0.5V[6] VCC= Max., VIN = GND Outputs Open
[4]
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V @ f = 1 MHz VOUT = 2.0 V @ f = 1 MHz Max. 10 10 Unit pF pF
Notes: 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 5. Tested initially and after any design or process changes that may affect these parameters. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Document #: 38-03012 Rev. **
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PLDC20RA10
AC Test Loads and Waveforms (Commercial)
R1 457 (470 MIL) 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 270 5 pF (319 Mil) INCLUDING JIG AND SCOPE GND R2 270 < 5 ns (319 Mil) R1 457 (470 MIL) ALL INPUT PULSES 3.0V 90% 10% 90% 10% < 5 ns
RA10-14
RA10-15
(a)
Equivalent to: OUTPUT 170
(b)
Equivalent to:
RA10-16
THEVENIN EQUIVALENT(Commercial) 1.86V=V thc
THEVENIN EQUIVALENT(Military) OUTPUT 190 2.02V=V thc
RA10-17
Parameter t PXZ(-) t PXZ(+) t PZX(+) t PZX(-) t ER(-) t ER(+) t EA(+) t EA(-)
Vth 1.5V 2.6V
Output W aveform Measurement Level V OH VX VX
RA10-19
0.5V 0.5V 0.5V
RA10-18
V OL VX VX V OH
V thc V thc 1.5V 2.6V V thc V thc
V OH
RA10-20
0.5V 0.5V 0.5V 0.5V
V OL VX VX
RA10-21
RA10-22
V OL VX VX (c)
RA10-23
V OH
RA10-24
0.5V
V OL
RA10-25
Document #: 38-03012 Rev. **
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PLDC20RA10
Switching Characteristics Over the Operating Range[3, 7, 8]
Commercial -15 Parameter tPD tEA tER tPZX tPXZ tCO tSU tH tP tWH tWL fMAX tS tR Description Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Pin 13 to Output Enable Pin 13 to Output Disable Clock to Output Input or Feedback Set-Up Time Hold Time Clock Period (tSU + tCO) Clock Width HIGH[5] Clock Width LOW
[5]
Military -20 Min. Max. 20 20 20 15 15 20 10 3 30 12 12 33.3 20 20 20 20 15 5 40 18 18 25.0 25 25 20 20 20 15 15 20 -25 Min. Max. 25 30 30 20 20 25 20 5 55 25 25 18.1 40 40 -35 Min. Max. 35 35 35 25 25 35 Unit ns ns ns ns ns ns ns ns ns ns ns MHz ns ns Max.
-20 Min. 15 15 15 12 12 15
Min.
Max.
7 3 22 10 10 45.5 15 15
10 5 30 13 13 33.3
Maximum Frequency (1/tP)[5] Input of Asynchronous Set to Registered Output Input of Asynchronous Reset to Registered Output Asynchronous Reset Width[5] Asynchronous S-Width[5] Asynchronous Set/ Reset Recovery Time Preload Pulse Width Preload Set-Up Time Preload Hold Time
tARW tASW tAR tWP tSUP tHP
15 15 10 15 15 15
20 20 12 15 15 15
20 20 12 15 15 15
25 25 15 15 15 15
25 25 20 15 15 15
ns ns ns ns ns ns
Notes: 7. Part (a) of AC Test Loads was used for all parameters except tEA, tER, tPZX and tPXZ, which use part (b). 8. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled HIGH output or VOL +0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
Document #: 38-03012 Rev. **
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PLDC20RA10
Switching Waveform
INPUTS,REGISTERED FEEDBACK t SU CP ASYNCHRONOUS RESET ASYNCHRONOUS SET OUTPUTS (HIGHASSERTED) OUTPUT ENABLE INPUTPIN t WH t AR t WL tH
tP
tPD t CO t ER t EA
RA10-26
Preload Switching Waveform
PIN 13 OUTPUT ENABLE REGISTER OUTPUTS PIN 1 PRELOAD CLOCK
t ER t EA t SUP t HP
t WP
RA10-27
Asynchronous Reset
ASYNCHRONOUS RESET OUTPUT
RA10-28
t ARW tR
Asynchronous Set
ASYNCHRONOUS SET tS OUTPUT
RA10-29
tASW
Document #: 38-03012 Rev. **
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PLDC20RA10
Functional Logic Diagram
Document #: 38-03012 Rev. **
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PLDC20RA10
Ordering Information
ICC2 80 tPD (ns) 15 tSU (ns) 7 tCO (ns) 15 Ordering Code PLDC20RA10-15JC PLDC20RA10-15PC CG7C324-A15JC 20 85 20 25 35 10 10 15 20 20 20 25 35 PLDC20RA10-20PC CG7C324-A20JC PLDC20RA10-20DMB PLDC20RA10-20WMB PLDC20RA10-25DMB PLDC20RA10-25WMB PLDC20RA10-35DMB PLDC20RA10-35WMB Package Name J64 P13 J64 P13 J64 D14 W14 D14 W14 D14 W14 Package Type 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Windowed CerDIP Military Operating Range Commercial
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
DC Characteristics
Parameter ICC Subgroups 1, 2, 3
Switching Characteristics
Parameter tPD tPZX tCO tSU tH Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
Document #: 38-03012 Rev. **
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PLDC20RA10
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9Config.A
28-Lead Plastic Leaded Chip Carrier J64
28-Square L64 Carrier Chip Leadless
MIL-STD-1835 C-4
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
Document #: 38-03012 Rev. **
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PLDC20RA10
Package Diagrams (continued)
28-Pin Windowed Leaded Chip Carrier H64
Document #: 38-03012 Rev. **
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PLDC20RA10
Package Diagrams (continued)
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D- 9 Config.A
Document #: 38-03012 Rev. **
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(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PLDC20RA10
Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Document Number: 38-03012 REV. ** ECN NO. 106294 Issue Date 04/24/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00073 to 38-03012
Document #: 38-03012 Rev. **
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